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dg641/642/643 vishay siliconix document number: 70058 s-52433?rev. e, 06-sep-99 www.vishay.com 1 low on-resistance wideband/video switches

wide bandwidth: 500 mhz low crosstalk at 5 mhz: ?85 db low r ds(on) : 5 , dg642 ttl logic compatible fast switching: t on 50 ns single supply compatibility high current: 100 ma, dg642 high precision improved frequency response low insertion loss improved system performance reduced board space low power consumption rf and video switching rgb switching video routing cellular communications ate radar/flir systems satellite receivers programmable filters

the dg641/642/643 are high performance monolithic video switches designed for switching wide bandwidth analog and digital signals. dg641 is a quad spst, dg642 is a single spdt, and DG643 is a dual spdt function. these devices have exceptionally low on-resistances (5 typ?dg642), low capacitance and high current handling capability. to achieve ttl compatibility, low channel capacitances and fast switching times, the dg641/642/643 are built on the vishay siliconix proprietary d/cmos process. each switch conducts equally well in both directions when on, and blocks up to 14 v p-p when off. an epitaxial layer prevents latchup.

sw 1 , sw 2 off on dg641 in 1 in 2 d 1 d 2 s 1 s 2 v? v+ gnd gnd s 4 s 3 d 4 d 3 in 4 in 3 dual-in-line and soic 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view logic ?0? 0.8 v logic ?1? 2.4 v logic switch 0 1 off on logic ?0? 0.8 v logic ?1? 2.4 v logic sw 2 0 1 on off logic ?0? 0.8 v logic ?1? 2.4 v logic 0 1 dg642 d 2 gnd dual-in-line and soic s 2 s 1 in d 1 v+ v? 1 2 3 4 8 7 6 5 top view 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 gnd gnd s 1 s 2 v? v+ s 4 s 3 gnd gnd d 4 d 3 dual-in-line and soic DG643 sw 1 off on sw 3 , sw 4 on off
dg641/642/643 vishay siliconix www.vishay.com 2 document number: 70058 s-52433 ? rev. e, 06-sep-99

temp range package part number dg641 16-pin plastic dip dg641dj ? 40 to 85 c 16-pin narrow soic dg641dy dg642 8-pin plastic dip dg642dj ? 40 to 85 c 8-pin narrow soic dg642dy DG643 16-pin plastic dip DG643dj ? 40 to 85 c 16-pin narrow soic DG643dy

v+ to v ?? 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to gnd ? 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ? to gnd ? 19 v to +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs (v ? ) ? 0.3 v to (v+) +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first v s , v d (v ? ) ? 0.3 v to (v ? ) +14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first continuous current (any terminal except s or d) 20 ma . . . . . . . . . . . . . . . . continuous current s or d: dg641/643 75 ma . . . . . . . . . . . . . . . . . . . . . . . dg642 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . current, s or d (pulsed 1 ms, 10% duty cycle max) dg641/643 200 ma . . . . . . . . . . . . . . . . . . . . . . dg642 300 ma . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature ? 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) b 8-pin plastic dip and narrow soic c 300 mw . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin plastic dip d 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow soic e 600 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 7.6 mw/ c above 75 c d. derate 6 mw/ c above 75 c e. derate 80 mw/ c above 75 c

figure 1. d s v+ in v ? 5 v reg gnd
dg641/642/643 vishay siliconix document number: 70058 s-52433 ? rev. e, 06-sep-99 www.vishay.com 3

test conditions unless otherwise specified limits ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v v inh = 2.4 v, v inl = 0.8 v e temp a min b typ c max b unit analog switch v ? = ? 5 v, v+ = 12 v full ? 5 8 analog signal range dd v analog v ? = gnd, v+ = 12 v full 0 8 v drain-source on-resistance r ds(on) i s = ? 10 ma, v d = 0 v room full 8 15 20 r ds(on) match r ds(on) i s = ? 10 ma, v d = 0 v room 1 2 ? 10 ? 100 ? 0.02 10 100 drain off leakage current i d(off) v s = 10 v, v d = 0v room full ? 10 ? 100 ? 0.02 10 100 na channel on leakage current i d(on) v s = v d = 0 v room full ? 10 ? 100 ? 0.1 10 100 digital control input voltage high v inh full 2.4 input voltage low v inl full 0.8 v input current i in v in = gnd or v+ room full ? 1 ? 20 0.05 1 20 a dynamic characteristics on state input capacitance d c s(on) v s = v d = 0 v room 10 20 off state input capacitance d c s(off) v s = 0 v room 4 12 pf off state output capacitance d c d(off) v d = 0 v room 4 12 bandwidth bw r l = 50 , see figure 6 room 500 mhz turn on time t on , c l = 35 pf, see figure 2 room full 28 50 85 ns charge injection q c l = 1000 pf, v d = 0 v, see figure 3 room ? 19 pc off isolation oirr r in = 75 , r l = 75 f = 5 mhz see figure 4 room ? 60 all hostile crosstalk x talk(ah) r in = 10 , r l = 75 , f = 5 mhz see figure 5 room ? 87 db power supplies positive supply current i+ room full 3.5 6 9 negative supply current i ? v in = 0 v or v in = 5 v room full ? 6 ? 9 ? 3 ma notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function.
dg641/642/643 vishay siliconix www.vishay.com 4 document number: 70058 s-52433 ? rev. e, 06-sep-99

test conditions unless otherwise specified limits ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 3 v v inh = 2.4 v, v inl = 0.8 v e temp a min b typ c max b unit analog switch v ? = ? 5 v, v+ = 12 v full ? 5 8 analog signal range d v analog v ? = gnd, v+ = 12 v full 0 8 v drain-source on-resistance r ds(on) i s = ? 10 ma, v d = 0 v room full 5 8 9 r ds(on) match r ds(on) i s = ? 10 ma, v d = 0 v room 0.5 1 ? 10 ? 200 ? 0.04 10 200 drain off leakage current i d(off) v s = 10 v, v d = 0v room full ? 10 ? 200 ? 0.04 10 200 na channel on leakage current i d(on) v s = v d = 0 v room full ? 10 ? 200 ? 0.2 10 200 digital control input voltage high v inh full 2.4 input voltage low v inl full 0.8 v input current i in v in = gnd or v+ room full ? 1 ? 20 0.05 1 20 a dynamic characteristics on state input capacitance d c s(on) v s = v d = 0 v room 19 40 off state input capacitance d c s(off) v s = 0 v room 8 20 pf off state output capacitance d c d(off) v d = 0 v room 8 20 bandwidth bw r l = 50 , see figure 6 room 500 mhz turn on time t on , c l = 35 pf, see figure 2 room full 40 60 100 ns charge injection q c l = 1000 pf, v d = 0 v, see figure 3 room ? 40 pc off isolation r in = 75 , r l = 75 f = 5 mhz see figure 4 room ? 63 all hostile crosstalk x talk(ah) r in = 10 , r l = 75 , f = 5 mhz see figure 5 room ? 85 db power supplies positive supply current i+ room full 3.5 6 9 negative supply current i ? v in = 0 v or v in = 5 v room full ? 6 ? 9 ? 3 ma notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function.
dg641/642/643 vishay siliconix document number: 70058 s-52433 ? rev. e, 06-sep-99 www.vishay.com 5

6 5 4 3 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 55 ? 35 ? 15 5 25 45 65 85 105 125 i + i ? supply current vs. temperature i gnd temperature ( c) current (ma) ? 55 0 125 100 na 10 na 1 na 100 pa 10 pa 1 pa leakages vs. temperature temperature ( c) i d(off) ,i s(off) 0.1 pa ? 25 25 50 75 100 20 15 10 5 0 ? 3 ? 11 35 7911 v+ = 15 v v ? = ? 3 v dg642 r ds(on) vs. drain voltage v d ? drain voltage (v) 125 c 25 c ? 55 c 1 10 100 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 oirr (db) f ? frequency (mhz) dg641/643 dg642 off isolation 22 20 18 16 14 12 10 8 6 12 10 8 6 4 2 0 c (pf) (v d ) ? (v ? ) dg642 dg641/643 on capacitance 40 30 20 10 0 ? 3 ? 11 35 7 911 v+ = 15 v v ? = ? 3 v 125 c 25 c ? 55 c dg641/643 r ds(on) vs. drain voltage r ds(on) ? drain-source on-resistance ( v d ? drain voltage (v) r ds(on) ? drain-source on-resistance ( ) )
dg641/642/643 vishay siliconix www.vishay.com 6 document number: 70058 s-52433 ? rev. e, 06-sep-99

? 55 0 125 ? 25 25 50 75 100 10 12 14 16 18 20 ? 4 ? 3 ? 2 ? 1 0 operating voltage area v+ ? positive supply voltage (v) ? 6 ? 5 1 10 100 110 100 90 80 70 60 50 40 30 20 10 (db) x talk all hostile crosstalk f ? frequency (mhz) dg642 dg641/643 0 ? 10 ? 20 ? 30 ? 40 8 4 2 0 ? 2 ? 36 ? 11 357 q (pc) charge injection vs. v d dg642 dg641/643 c l = 1000 pf 90 70 60 50 40 30 20 10 0 80 switching times vs. temperature t (ns) temperature ( c) t on t off v d ? drain voltage (v) v ? ? negative supply (v) operating supply voltage range
dg641/642/643 vishay siliconix document number: 70058 s-52433 ? rev. e, 06-sep-99 www.vishay.com 7

figure 2. switching time figure 3. charge injection 3 v 0 90% 90% 50% t off t on t r <20 ns t f <20 ns logic input switch output on on off v o v o in x v o = measured voltage error due to charge injection the charge injection in coulombs is q = c l x v o figure 4. off isolation 3 v v ? v+ in s c l 35 pf d 3 v r l 1 k v o ? 3 v gnd +15 v c l 1000 pf 3 v v g v o d v+ r g s in v ? ? 3 v gnd +15 v s in r l d r g = 50 v s v o 0v, 2.4 v off isolation = 20 log v s v o v+ ? 3 v gnd v ? c c +15 v
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figure 5. all hostile crosstalk ? x talk(ah) signal generator 75 s 1 s 2 ? 0 ? v out r l 75 r l r l r l r in 10 s 1 s 2 s 3 s 4 ? 1 ? d 1 d 2 d 3 d 4 signal generator 75 r in 10 v (a) dg641 (b) dg642 r l d 1 d 2 v +15 v ? 3 v v+ v ? signal generator 50 v out r l 50 sd figure 6. bandwidth v out r l 75 x talk(ah) 20 log 10 v out v

device description the dg641/642/643 switches offer true bidirectional switching of high frequency analog or digital signals with minimum signal crosstalk, low insertion loss, and negligible non-linearity distortion and group delay. built on the siliconix d/cmos process, these switches provide excellent off-isolation with a bandwidth of around 500 mhz. the silicon-gate d/cmos processing also yields fast switching speeds. an on-chip regulator circuit maintains ttl input compatibility over the whole operating supply voltage range shown, easing control logic interfacing. circuit layout is facilitated by the interchangeability of source and drain terminals. frequency response a single switch on-channel exhibits both resistance [r ds(on) ] and capacitance [c s(on) ]. this rc combination has an attenuation effect on the analog signal ? which is frequency dependent (like an rc low-pass filter). the ? 3 db bandwidth of the dg641/642/643 is typically 500 mhz (into 50
dg641/642/643 vishay siliconix document number: 70058 s-52433 ? rev. e, 06-sep-99 www.vishay.com 9

power supplies power supply flexibility is a useful feature of the dg641/642/643 series. it can be operated from a single positive supply (v+) if required (v ? connected to ground). note that the analog signal must not exceed v ? by more than ? 0.3 v to prevent forward biasing the substrate p-n junction. the use of a v ? supply has a number of advantages: 1. it allows flexibility in analog signal handling, i.e., with v ? = ? 5 v and v+ = 12 v; up to 5-v ac signals can be controlled. 2. the value of on capacitance [c s(on) ] may be reduced. a property known as ? the body-effect ? on the dmos switch devices causes various parametric effects to occur. one of these effects is the reduction in c s(on) for an increasing v body-source. note however that to increase v ? normally requires v+ to be reduced (since v+ to v ? = 21 v max.). a reduction in v+ causes an increase in r ds(on) , hence a compromise has to be achieved. it is also useful to note that tests indicate that optimum video linearity performance (e.g., differential phase and gain) occurs when v ? is around ? 3 v. 3. v ? eliminates the need to bias the analog signal using potential dividers and large coupling capacitors. decoupling it is an established rf design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. the dynamic performance of the dg641/642/643 series is adversely affected by poor decoupling of power supply pins. also, of even more significance, since the substrate of the device is connected to the negative supply, adequate decoupling of this pin is essential. suitable decoupling capacitors are 1- to 10- f tantalum bead, plus 10- to 100-nf ceramic or polyester. rules: 1. decoupling capacitors should be incorporated on all power supply pins (v+, v ? ). (see figure 7). 2. they should be mounted as close as possible to the device pins. 3. capacitors should be of a suitable type with good high frequency characteristics ? tantalum bead and/or ceramic disc types are adequate. + + ? 3 v gnds +15 v dg64x v+ v ? s 1 s 2 s 3 s 4 d 1 d 2 d 3 d 4 c 1 c 2 c 1 c 2 c 1 = 10 f tantalum c 2 = 0.1 f ceramic figure 7. supply decoupling board layout pcb layout rules for good high frequency performance must also be observed to achieve the performance boasted by these analog switches. some tips for minimizing stray effects are: 1. use extensive ground planes on double sided pcb, separating adjacent signal paths. multilayer pcb is even better. 2. keep signal paths as short as practically possible, with all channel paths of near equal length. 3. careful arrangement of ground connections is also very important. star connected system grounds eliminate signal current, flowing through ground path parasitic resistance, from coupling between channels. figure 8 shows a 4-channel video multiplexer using a dg641. in figure 9, two coax cables terminated on 75 bring two video signals to the dg642 switch. the two drains tied together lower the on-state capacitance. an si582 video amplifier drives a double terminated 75- cable. the double terminated coax cable eliminates line reflections.
dg641/642/643 vishay siliconix www.vishay.com 10 document number: 70058 s-52433 ? rev. e, 06-sep-99

+ ? +15 v v+ v ? ? 3 v ttl channel select a = 2 75 250 si582 ch 1 ch 2 ch 3 ch 4 dg641 dis 75 75 75 75 250 + ? +15 v v+ v ? ? 3 v ttl channel select a = 2 si582 ch 1 ch 2 dg642 dis 250 75 250 75 r l 75 75 v out s 1 s 2 d 1 d 2 fc 1 2 r 3 c x fc select in 2 s 2 s 3 d 2 d 3 c 1 c 2 r 3 1 / 2 DG643 r 1 r 2 v out s 1 s 4 d 1 d 4 in 1 ch 1 ch 2 ch select lf401 ? + figure 8. 4 by 1 video multiplexing using the dg641 figure 9. 2-channel video selector using the dg642 figure 10. active low pass filter with selectable inputs and break frequencies 1 / 2 DG643

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